1. Field of the Invention
The present invention relates to a digital signal measuring apparatus and its observing method for observing the signal traffic on a bus of a system to be measured.
2. Background of the Invention
Conventionally, the observation and evaluation of a digital bus are generally performed in the following way.
While using a digital signal measuring apparatus such as a logic analyzer, a bus is probed and triggered with a predetermined bus pattern, then a digital bus signal is acquired, and the obtained data of digital bus signal is stored in a digital storage equipped for the logic analyzer. At the same time, the measurement result of this digital signal is displayed in waveform on a display.
In the case where the measurement result is observed and analyzed in detail, an analysis program is executed for the acquired data stored in the digital storage on a computer.
A conventional digital signal measuring apparatus for observing the digital bus is exemplified below.
FIG. 8 is a block diagram illustrating the configuration of the logic analyzer. In the same figure, two logic analyzers 810A and 810B are shown to observe two buses 820A and 820B, each logic analyzer having the same configuration.
Referring to FIG. 8, the logic analyzers 810A and 810B are connected to the probes 830 for acquiring a digital bus signal from the buses 820A and 820B, respectively, and comprise a trigger generating device 811 for timing the acquisition of the digital bus signal, a digital storage 812 for storing the data of acquired digital bus signal, and a display 813 for displaying the data.
The logic analyzers 810A and 810B observe the buses 820A and 820B, respectively, as shown in FIG. 8. The logic analyzers 810A and 810B are interconnected externally, in which the logic analyzer 810B is triggered upon a synchronizing signal from the logic analyzer 810A.
In Published Unexamined Japanese Patent Application No. 11-344511, a technique regarding a logic analyzer probe circuit that is interposed between the logic analyzer and a measured circuit measured by the logic analyzer was disclosed.
FIG. 9 is a block diagram showing the configuration of the logic analyzer probe circuit as described in the above patent.
Referring to FIG. 9, this logic analyzer probe circuit 910 comprises a probe circuit 911 for converting a signal input from a measurement point of a measured circuit 920 into electrical specification and outputting the converted signal, and a logic operation section (programmable gate array) 912 for inputting an output signal from the probe circuit 911, making a predetermined logical operation on the signal, and outputting a result of logical operation to a logic analyzer 930.
FIG. 10 is a block diagram showing the configuration of a PCI bus monitor as another conventional digital signal measuring apparatus.
In FIG. 10, if a bus monitor device 1010 is inserted into a PCI bus 1020 of a system to be measured, the bus monitor device 1010 acquires a digital bus signal passed on the PCI bus 1020, and stores the data of measurement result in a digital storage (SRAM) 1011 mounted in the bus monitor device 1010. After the end of measurement, the measurement result stored in the digital storage 1011 is transferred to a computer as an analyzer connected externally, and the computer executes a specific analysis program to produce the analysis result.
However, with a recent increase in the system bus width, the data amount that must be stored per unit time in measurement of the digital bus has become enormous.
From only the viewpoint of the data amount to be stored, an external storage (e.g., magnetic disk) may be additionally mounted outside the measuring apparatus, but when the system bus clock is fast; the data can not be written without delay because the external storage has a low write rate. Therefore, there is a need that the measuring apparatus mounts a digital storage (e.g., semiconductor memory) capable of writing fast internally.
The fast digital storage is expensive, and physically mountable with a limited capacity. Accordingly, in the present situation where the amount of data to be stored increases, the conventional digital signal measuring apparatus is difficult to perform the continuous observation and evaluation over the long time.
On one hand, for the evaluation and analysis of the total system, it is indispensable to make the observation over the long time. Also, it is indispensable to detect an unexpected bus event that must be observed over the long time to discover and evaluate its operation.
The conventional digital signal measuring apparatus acquired a digital bus signal on the bus, stored it in the digital storage, analyzed the stored digital bus signal to extract a bus event, and observed the signal traffic on the bus. Therefore, it was impossible to observe the signal traffic on the bus in real time in accordance with the operation of the system to be measured.
Further, in case of observing plural buses, due to the recent increase in the bus width, there are some instances where the number of buses to be measured exceeds the number of probes mountable on one logic analyzer. In this case, a plurality of logic analyzers are prepared, interconnected externally, and synchronized, as shown in FIG. 8.
However, the external connection through the cable is liable to produce more noise to cause the malfunction as the signal frequency is increased.